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142 lines
3.7 KiB

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:19:20 05/03/2019
-- Design Name:
-- Module Name: /home/rani/Desktop/git/picoblaze-lab/tb2_vga.vhd
-- Project Name: picoblaze
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: toplevel
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb2_vga IS
END tb2_vga;
ARCHITECTURE behavior OF tb2_vga IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT toplevel
PORT(
port_id : OUT std_logic_vector(7 downto 0);
write_strobe : OUT std_logic;
read_strobe : OUT std_logic;
out_port : OUT std_logic_vector(7 downto 0);
in_port : OUT std_logic_vector(7 downto 0);
reset : IN std_logic;
clk : IN std_logic;
rx : IN std_logic;
tx : OUT std_logic;
LED : OUT std_logic;
R : OUT std_logic;
G : OUT std_logic;
B : OUT std_logic;
H : OUT std_logic;
V : OUT std_logic
);
END COMPONENT;
--Inputs
signal reset : std_logic := '0';
signal clk : std_logic := '0';
signal rx : std_logic := '0';
--Outputs
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal read_strobe : std_logic;
signal out_port : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal tx : std_logic;
signal LED : std_logic;
signal R : std_logic;
signal G : std_logic;
signal B : std_logic;
signal H : std_logic;
signal V : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: toplevel PORT MAP (
port_id => port_id,
write_strobe => write_strobe,
read_strobe => read_strobe,
out_port => out_port,
in_port => in_port,
reset => reset,
clk => clk,
rx => rx,
tx => tx,
LED => LED,
R => R,
G => G,
B => B,
H => H,
V => V
);
clk <= not clk after 10 ns;
reset <= '1', '0' after 200 ns;
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
rx <= '1'; --linea de recepcion inactiva
wait for 20 us;
rx <= '0'; --bit de inicio
wait for 8.68 us; --OJO: para transmitir a 9600 bps poner 104.16 us
-- para transmitir a 115200 bps poner 8.68 us
rx <= '1'; --enviamos una A (=0100.0001) --> Una A en ASCII
wait for 8.68 us;
rx <= '0';
wait for 8.68 us;
rx <= '0';
wait for 8.68 us;
rx <= '0';
wait for 8.68 us;
rx <= '0';
wait for 8.68 us;
rx <= '0';
wait for 8.68 us;
rx <= '1';
wait for 8.68 us;
rx <= '0';
wait for 8.68 us;
rx <= '1'; --bit de parada
wait for 8.68 us;
wait for 1000 ms;
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;