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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity controllerVGA is
port(
clk : in std_logic; -- Spartan 3E 50MHz de clk
hsync, vsync : out std_logic;
ready : out std_logic;
x : out std_logic_vector(9 downto 0);
y : out std_logic_vector(9 downto 0)
);
end controllerVGA;
architecture controllerVGA of controllerVGA is
constant h_displayArea : integer := 640;
constant h_limit : integer := 800;
constant h_frontPorch : integer := 16;
constant h_backPorch : integer := 47; -- default 48. Parece que funciona bien.
constant h_syncPulse : integer := 96;
constant v_displayArea : integer := 480;
constant v_limit : integer := 521;
constant v_frontPorch : integer := 10; -- default 10
constant v_backPorch : integer := 33; -- default 33. Con 28 parece que funciona OK
constant v_syncPulse : integer := 2;
-- Max valor será 800 (h_limit) 800 -> 1100100000
signal h_currentPos : std_logic_vector(9 downto 0) := (others=> '0');
-- Max valor sera 525 (v_limit) 525 -> 1000001101
signal v_currentPos : std_logic_vector(9 downto 0) := (others=> '0');
signal h_ready, v_ready : std_logic := '0';
-- Contamos los pixeles
signal countX, countY : std_logic_vector(9 downto 0) := (others => '0');
begin
-- Proceso de actualización de VGA. Barrido de sincronizacion hor/ver
sync: process(clk)
variable clock_25 : std_logic := '0';
begin
if(rising_edge(clk)) then
if clock_25 = '1' then
if h_currentPos < h_limit-1 then
-- Aumentamos el contador Horizontal.
h_currentPos <= h_currentPos+1;
-- Primero hacemos una linea horizontal, y despues aumentamos
-- una vertical
else
if v_currentPos < v_limit-1 then
-- Aumentamos el contador Vertical.
v_currentPos <= v_currentPos+1;
else
v_currentPos <= (others => '0');
end if;
-- Reiniciamos el contador horizontal
h_currentPos <= (others => '0');
end if;
end if;
clock_25 := NOT clock_25;
end if;
end process;
-- Sincronizacion Horizontal
hsync <= '0' when h_currentPos < h_syncPulse else '1';
-- Sincronizacion Vertical
vsync <= '0' when v_currentPos < v_syncPulse else '1';
-- Ready signals
h_ready <= '1' when (h_currentPos >= h_syncPulse+h_backPorch) AND
(h_currentPos < h_syncPulse+h_backPorch+h_displayArea) else '0';
v_ready <= '1' when (v_currentPos >= v_syncPulse+v_backPorch) AND
(v_currentPos < v_syncPulse+v_backPorch+v_displayArea) else '0';
ready <= h_ready AND v_ready;
-- Cuenta de pixeles del area visible
countX <= h_currentPos-h_syncPulse-h_backPorch when h_ready = '1' else (others => '0');
x <= countX;
countY <= v_currentPos-v_syncPulse-v_backPorch when v_ready = '1' else (others => '0');
y <= countY;
end architecture;