Browse Source

synthesize OK. tb checking OK

master
Enrique Fernandez 3 years ago
parent
commit
8012e63677
  1. 17
      controllerVGA.vhd
  2. 9
      fuse.xmsgs
  3. BIN
      isim/temp/addsub8.vdb
  4. BIN
      isim/temp/arithmetic_process.vdb
  5. BIN
      isim/temp/carry_flag_logic.vdb
  6. BIN
      isim/temp/controllervga.vdb
  7. BIN
      isim/temp/interrupt_capture.vdb
  8. BIN
      isim/temp/interrupt_logic.vdb
  9. BIN
      isim/temp/io_strobe_logic.vdb
  10. BIN
      isim/temp/logical_bus_processing.vdb
  11. BIN
      isim/temp/picoblaze.vdb
  12. BIN
      isim/temp/program_counter.vdb
  13. BIN
      isim/temp/programa_helloworld.vdb
  14. BIN
      isim/temp/ram_nx1.vdb
  15. BIN
      isim/temp/ram_x1s.vdb
  16. BIN
      isim/temp/register_and_flag_enable.vdb
  17. BIN
      isim/temp/register_bank.vdb
  18. BIN
      isim/temp/shift_rotate.vdb
  19. BIN
      isim/temp/stack_counter.vdb
  20. BIN
      isim/temp/stack_ram.vdb
  21. BIN
      isim/temp/t_state_and_reset.vdb
  22. BIN
      isim/temp/tb2_vga.vdb
  23. BIN
      isim/temp/toplevel.vdb
  24. BIN
      isim/temp/zero_flag_logic.vdb
  25. 107
      picoblaze.xise
  26. 140
      tb2_vga.vhd
  27. 45
      toplevel.vhd
  28. 1
      xilinxsim.ini

17
controllerVGA.vhd

@ -25,7 +25,7 @@ architecture controllerVGA of controllerVGA is
constant v_limit : integer := 525;
constant v_frontPorch : integer := 10;
constant v_backPorch : integer := 33;
constant v_syncPulse : integer 2;
constant v_syncPulse : integer := 2;
signal s_clk_25 : std_logic := '0'; -- Empieza en 0.
@ -43,7 +43,7 @@ begin
-- Divisor de frecuencia para obtener la frecuencia de muestreo del VGA
-- Entrada CLK 50MHz -> Salida 25MHz
clk25MHz: process(clk):
clk25MHz: process(clk)
begin
if(rising_edge(clk)) then
s_clk_25 <= NOT s_clk_25;
@ -52,20 +52,21 @@ begin
clk_25 <= s_clk_25;
-- Proceso de actualización de VGA. Barrido de sincronizacion hor/ver
sync: process(s_clk_25):
sync: process(s_clk_25)
begin
if(rising_edge(s_clk_25)) then
if h_currentPos < h_limit - 1 then
-- Aumentamos el contador Horizontal.
h_currentPos <= h_currentPos + 1;
-- Primero hacemos una linea horizontal, y despues aumentamos
-- una vertical
else
if v_currentPos < v_limit - 1 then
-- Aumentamos el contador Vertical.
v_currentPos <= v_currentPos + 1;
else
v_currentPos <= (others => '0');
if v_currentPos < v_limit - 1 then
-- Aumentamos el contador Vertical.
v_currentPos <= v_currentPos + 1;
else
v_currentPos <= (others => '0');
end if;
-- Reiniciamos el contador horizontal

9
fuse.xmsgs

@ -0,0 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

BIN
isim/temp/addsub8.vdb

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isim/temp/arithmetic_process.vdb

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isim/temp/carry_flag_logic.vdb

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isim/temp/controllervga.vdb

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isim/temp/interrupt_capture.vdb

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isim/temp/interrupt_logic.vdb

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isim/temp/io_strobe_logic.vdb

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isim/temp/logical_bus_processing.vdb

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isim/temp/picoblaze.vdb

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isim/temp/program_counter.vdb

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isim/temp/programa_helloworld.vdb

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isim/temp/ram_nx1.vdb

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isim/temp/ram_x1s.vdb

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isim/temp/register_and_flag_enable.vdb

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isim/temp/register_bank.vdb

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isim/temp/shift_rotate.vdb

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isim/temp/stack_counter.vdb

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isim/temp/stack_ram.vdb

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isim/temp/t_state_and_reset.vdb

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isim/temp/tb2_vga.vdb

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isim/temp/toplevel.vdb

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isim/temp/zero_flag_logic.vdb

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107
picoblaze.xise

@ -16,79 +16,85 @@
<files>
<file xil_pn:name="arithmatic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="carry_flag_logic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="interrupt_capture.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="interrupt_logic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="IO_strobe_logic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="logical_bus_processing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="picoblaze.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="program_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="register_and_flag_enable.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="register_bank.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="shift_rotate.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="stack_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="stack_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="T_state_and_Reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="zero_flag_logic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="PicoBlaze_s3estarter.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="toplevel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="programa_helloworld.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<file xil_pn:name="projectVGA.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="controllerVGA.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="tb2_vga.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="33"/>
</file>
</files>
@ -195,9 +201,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="tb.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|toplevel|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="toplevel.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/toplevel" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -255,7 +261,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="tb" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="toplevel" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@ -267,10 +273,10 @@
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="tb_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="tb_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="tb_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="tb_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="toplevel_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="toplevel_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="toplevel_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="toplevel_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
@ -290,7 +296,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="tb" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="toplevel" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
@ -314,7 +320,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb2_vga" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb2_vga" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@ -330,7 +337,7 @@
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb2_vga" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@ -379,7 +386,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|tb2_vga|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="picoblaze" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

140
tb2_vga.vhd

@ -0,0 +1,140 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:19:20 05/03/2019
-- Design Name:
-- Module Name: /home/rani/Desktop/git/picoblaze-lab/tb2_vga.vhd
-- Project Name: picoblaze
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: toplevel
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb2_vga IS
END tb2_vga;
ARCHITECTURE behavior OF tb2_vga IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT toplevel
PORT(
port_id : OUT std_logic_vector(7 downto 0);
write_strobe : OUT std_logic;
read_strobe : OUT std_logic;
out_port : OUT std_logic_vector(7 downto 0);
in_port : OUT std_logic_vector(7 downto 0);
reset : IN std_logic;
clk : IN std_logic;
rx : IN std_logic;
tx : OUT std_logic;
LED : OUT std_logic;
R : OUT std_logic;
G : OUT std_logic;
B : OUT std_logic;
H : OUT std_logic;
V : OUT std_logic
);
END COMPONENT;
--Inputs
signal reset : std_logic := '0';
signal clk : std_logic := '0';
signal rx : std_logic := '0';
--Outputs
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal read_strobe : std_logic;
signal out_port : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal tx : std_logic;
signal LED : std_logic;
signal R : std_logic;
signal G : std_logic;
signal B : std_logic;
signal H : std_logic;
signal V : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: toplevel PORT MAP (
port_id => port_id,
write_strobe => write_strobe,
read_strobe => read_strobe,
out_port => out_port,
in_port => in_port,
reset => reset,
clk => clk,
rx => rx,
tx => tx,
LED => LED,
R => R,
G => G,
B => B,
H => H,
V => V
);
clk <= not clk after 10 ns;
reset <= '1', '0' after 200 ns;
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
rx <= '1'; --linea de recepcion inactiva
wait for 20 us;
rx <= '0'; --bit de inicio
wait for 8.68 us; --OJO: para transmitir a 9600 bps poner 104.16 us
-- para transmitir a 115200 bps poner 8.68 us
rx <= '1'; --enviamos una A (=0100.0001) --> Una A en ASCII
wait for 8.68 us;
rx <= '0';
wait for 8.68 us;
rx <= '0';
wait for 8.68 us;
rx <= '0';
wait for 8.68 us;
rx <= '0';
wait for 8.68 us;
rx <= '0';
wait for 8.68 us;
rx <= '1';
wait for 8.68 us;
rx <= '0';
wait for 8.68 us;
rx <= '1'; --bit de parada
wait for 8.68 us;
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;

45
toplevel.vhd

@ -79,18 +79,16 @@ x"2A", x"0A", x"0D", x"00", x"00", x"00", x"00", x"00" );
signal rxbuff_out,RAM_out: std_logic_vector(7 downto 0);
-- VGA signals
constant h_displayArea : integer := 640;
constant v_displayArea : integer := 480;
signal x, y : std_logic_vector(9 downto 0);
signal clk_25 : std_logic;
signal ready : std_logic;
signal r,g,b : std_logic;
signal hsync, vsync : std_logic;
signal xCount, yCount : integer;
-- Añadimos el controlador de VGA
component controllerVGA
port (
clk : in std_logic;
clk_25 : out std_logic;
hsync, vsync : out std_logic;
ready : out std_logic;
x : out std_logic_vector(9 downto 0);
@ -131,43 +129,44 @@ begin
vga:controllerVGA
port map( clk => clk,
clk_25 => clk_25;
hsync => hsync,
vsync => vsync,
clk_25 => clk_25,
hsync => H,
vsync => V,
ready => ready,
x => x, -- X es la cuenta de la posicion
y => y); -- Y es la cuenta de la posicion
-- Cambiamos a unsigned para poder hacer comparaciones dentro de los procesos
xCount <= to_integer(unsigned(x));
yCount <= to_integer(unsigned(y));
-- TODO: Proceso controlador del VGA. SIN COMPROBAR!!!
vga:process(clk25)
process(clk_25)
-- Variable para los colores. CARGA INSTANTANEA DEL VALOR, SOLO PARA USO TEMPORAL!!
variable RGB : std_logic_vector(2 downto 0) := (others => '0');
begin
if rising_edge(clk25) then
if rising_edge(clk_25) then
if reset = '1' then
hsync <= '1';
vsync <= '1';
RGB := (others => '0');
else
-- Si estamos dentro del rango de display
if (x < h_displayArea AND y < v_displayArea) then
if (xCount < 640 AND yCount < 480) then
-- Default color como black
RGB := (others => '0');
-- Dibujamos un borde de 2px en LEFT
if x>= 0 AND x<2 then
if xCount >= 0 AND xCount < 2 then
RGB := "1" & "1" & "0";
-- Dibujamos un borde de 2px en RIGHT
elsif x<= h_displayArea - 1 AND x > h_displayArea - 3 then
elsif xCount <= 639 AND xCount > 637 then
RGB := "1" & "1" & "0";
end if;
-- Dibujamos borde de 2px en TOP
if y>=0 AND y<2 then
if yCount >=0 AND yCount < 2 then
RGB := "1" & "1" & "0";
-- Dibujamos borde de 2px en BOT
elsif y<= v_displayArea - 1 AND y > v_displayArea - 3 then
elsif yCount <= 479 AND yCount > 477 then
RGB := "1" & "1" & "0";
end if;
@ -179,18 +178,14 @@ begin
G <= RGB(1);
B <= RGB(0);
else
R <= "0";
G <= "0";
B <= "0";
R <= '0';
G <= '0';
B <= '0';
end if;
end if;
end if;
end process;
-- Mandamos la sincronziacion a los puertos de salida
H <= hsync;
V <= vsync;
--registra el bit tx del puerto de salida, por si éste cambia
-- Usamos el puerto FF.
txbuff:process(reset, clk)
@ -218,7 +213,7 @@ begin
end process;
-- Memoria RAM. Tipo => Escritura sincrona/Lectura asincrona
RAM:process(clk)
process(clk)
begin
if(clk'event and clk = '1') then
if(writestrobe = '1' and portid<x"40") then

1
xilinxsim.ini

@ -0,0 +1 @@
isim_temp=isim/temp
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