Browse Source

tb for vga simulator

master
Raniita 3 years ago
parent
commit
79ef356bba
  1. 2
      fuseRelaunch.cmd
  2. 16
      picoblaze.xise
  3. BIN
      tb2_vga_isim_beh.wdb
  4. 179
      tb_vga1.vhd
  5. BIN
      tb_vga1_isim_beh.exe
  6. BIN
      tb_vga1_isim_beh.wdb
  7. 26
      write.txt

2
fuseRelaunch.cmd

@ -1 +1 @@
-intstyle "ise" -incremental -o "/home/rani/Desktop/git/picoblaze-lab/tb2_vga_isim_beh.exe" -prj "/home/rani/Desktop/git/picoblaze-lab/tb2_vga_beh.prj" "work.tb2_vga"
-intstyle "ise" -incremental -o "/home/rani/Desktop/git/picoblaze-lab/tb_vga1_isim_beh.exe" -prj "/home/rani/Desktop/git/picoblaze-lab/tb_vga1_beh.prj" "work.tb_vga1"

16
picoblaze.xise

@ -87,7 +87,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="tb2_vga.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="33"/>
@ -96,6 +96,12 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="tb_vga1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="44"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="44"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="44"/>
</file>
</files>
<properties>
@ -320,8 +326,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb2_vga" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb2_vga" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_vga1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_vga1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@ -337,7 +343,7 @@
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb2_vga" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_vga1" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@ -386,7 +392,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|tb2_vga|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|tb_vga1|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="picoblaze" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

BIN
tb2_vga_isim_beh.wdb

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179
tb_vga1.vhd

@ -0,0 +1,179 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:32:27 05/03/2019
-- Design Name:
-- Module Name: /home/rani/Desktop/git/picoblaze-lab/tb_vga1.vhd
-- Project Name: picoblaze
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: toplevel
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_textio.all;
use std.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_vga1 IS
END tb_vga1;
ARCHITECTURE behavior OF tb_vga1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT toplevel
PORT(
port_id : OUT std_logic_vector(7 downto 0);
write_strobe : OUT std_logic;
read_strobe : OUT std_logic;
out_port : OUT std_logic_vector(7 downto 0);
in_port : OUT std_logic_vector(7 downto 0);
reset : IN std_logic;
clk : IN std_logic;
rx : IN std_logic;
tx : OUT std_logic;
LED : OUT std_logic;
R : OUT std_logic;
G : OUT std_logic;
B : OUT std_logic;
H : OUT std_logic;
V : OUT std_logic
);
END COMPONENT;
--Inputs
signal reset : std_logic := '0';
signal clk : std_logic := '0';
signal rx : std_logic := '0';
--Outputs
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal read_strobe : std_logic;
signal out_port : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal tx : std_logic;
signal LED : std_logic;
signal R : std_logic;
signal G : std_logic;
signal B : std_logic;
signal H : std_logic;
signal V : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: toplevel PORT MAP (
port_id => port_id,
write_strobe => write_strobe,
read_strobe => read_strobe,
out_port => out_port,
in_port => in_port,
reset => reset,
clk => clk,
rx => rx,
tx => tx,
LED => LED,
R => R,
G => G,
B => B,
H => H,
V => V
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
reset <= '1';
wait for 100 ns;
reset <= '0';
wait;
end process;
--Write process
process (clk)
file file_pointer: text is out "write.txt";
variable line_el: line;
begin
if rising_edge(clk) then
--line_el := "1";
-- Write the time
write(line_el, now); --write the line.
write(line_el, ":"); --write the line.
--writeline(file_pointer, line_el); --write the contents into the file.
-- Write the hsync
write(line_el, " ");
write(line_el, H); --write the line.
--writeline(file_pointer, line_el); --write the contents into the file.
-- Write the vsync
write(line_el, " ");
write(line_el, V); --write the line.
--writeline(file_pointer, line_el); --write the contents into the file.
-- Write the red
write(line_el, " ");
write(line_el, R); --write the line.
--writeline(file_pointer, line_el); --write the contents into the file.
-- Write the green
write(line_el, " ");
write(line_el, G); --write the line.
--writeline(file_pointer, line_el); --write the contents into the file.
-- Write the blue
write(line_el, " ");
write(line_el, B); --write the line.
writeline(file_pointer, line_el); --write the contents into the file.
end if;
end process;
END;

BIN
tb_vga1_isim_beh.exe

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BIN
tb_vga1_isim_beh.wdb

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26
write.txt

@ -0,0 +1,26 @@
10 ns: 0 0 U U U
30 ns: 0 0 1 1 0
50 ns: 0 0 1 1 0
70 ns: 0 0 1 1 0
90 ns: 0 0 1 1 0
110 ns: 0 0 1 1 0
130 ns: 0 0 1 1 0
150 ns: 0 0 1 1 0
170 ns: 0 0 1 1 0
190 ns: 0 0 1 1 0
210 ns: 0 0 1 1 0
230 ns: 0 0 1 1 0
250 ns: 0 0 1 1 0
270 ns: 0 0 1 1 0
290 ns: 0 0 1 1 0
310 ns: 0 0 1 1 0
330 ns: 0 0 1 1 0
350 ns: 0 0 1 1 0
370 ns: 0 0 1 1 0
390 ns: 0 0 1 1 0
410 ns: 0 0 1 1 0
430 ns: 0 0 1 1 0
450 ns: 0 0 1 1 0
470 ns: 0 0 1 1 0
490 ns: 0 0 1 1 0
510 ns: 0 0 1 1 0
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