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added new instruction

new
Raniita 3 years ago
parent
commit
46df4f924d
  1. 66
      flip.vhd
  2. 30
      picoblaze.vhd
  3. 34
      picoblaze.xise
  4. 6
      register_and_flag_enable.vhd

66
flip.vhd

@ -1,33 +1,33 @@
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit flip process
-- Operation
--
-- The input operand is flipped
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity flip is
Port (operand : in std_logic_vector(7 downto 0);
Y : out std_logic_vector(7 downto 0);
clk : in std_logic);
end flip;
--
architecture low_level_definition of flip is
begin
bus_width_loop: for i in 0 to 7 generate
begin
FF:
process (clk)
begin
if (clk'event and clk = '1') then
Y(i) <= operand(7-i);
end if;
end process FF;
end generate bus_width_loop;
--
end low_level_definition;
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit flip process
-- Operation
--
-- The input operand is flipped
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity flip is
Port (operand : in std_logic_vector(7 downto 0);
Y : out std_logic_vector(7 downto 0);
clk : in std_logic);
end flip;
--
architecture low_level_definition of flip is
begin
bus_width_loop: for i in 0 to 7 generate
begin
FF:
process (clk)
begin
if (clk'event and clk = '1') then
Y(i) <= operand(7-i);
end if;
end process FF;
end generate bus_width_loop;
--
end low_level_definition;

30
picoblaze.vhd

@ -87,7 +87,7 @@ constant shift_rotate_id : std_logic_vector(4 downto 0) := "10100";
--
-- added new instruction
-- flip
-- constant flip_id : std_logic_vector(4 downto 0) := "11111";
constant flip_id : std_logic_vector(4 downto 0) := "11111";
--
-- input/output group
constant input_p_to_x_id : std_logic_vector(4 downto 0) := "10000";
@ -158,11 +158,11 @@ component shift_rotate
--
-- Definition of flip process
--
--component flip
-- Port (operand : in std_logic_vector(7 downto 0);
-- Y : out std_logic_vector(7 downto 0);
-- clk : in std_logic);
-- end component;
component flip
Port (operand : in std_logic_vector(7 downto 0);
Y : out std_logic_vector(7 downto 0);
clk : in std_logic);
end component;
--
-- Definition of an 8-bit logical processing unit
--
@ -191,7 +191,7 @@ component register_and_flag_enable
Port (i_logical: in std_logic;
i_arithmetic: in std_logic;
i_shift_rotate: in std_logic;
-- i_flip: in std_logic; -- added new instruction
i_flip: in std_logic; -- added new instruction
i_returni: in std_logic;
i_input: in std_logic;
active_interrupt : in std_logic;
@ -357,7 +357,7 @@ signal i_input : std_logic;
signal i_output : std_logic;
-- added new instruction
-- signal i_flip : std_logic;
signal i_flip : std_logic;
signal conditional : std_logic;
@ -464,10 +464,10 @@ begin
clk => clk);
-- added new instruction
-- flip_group: flip
-- port map (operand => sX_register,
-- Y => flip_result,
-- clk => clk);
flip_group: flip
port map (operand => sX_register,
Y => flip_result,
clk => clk);
logical_group: logical_bus_processing
port map (first_operand => sX_register,
@ -490,7 +490,7 @@ begin
Port map (i_logical => i_logical,
i_arithmetic => i_arithmetic,
i_shift_rotate => i_shift_rotate,
-- i_flip => i_flip, -- added new instruction
i_flip => i_flip, -- added new instruction
i_returni => i_returni,
i_input => i_input,
active_interrupt => active_interrupt,
@ -652,7 +652,7 @@ begin
i_shift_rotate <= '1' when instruction(15 downto 11) = shift_rotate_id else '0';
-- added new instruction
-- i_flip <= '1' when instruction(15 downto 11) = flip_id else '0';
i_flip <= '1' when instruction(15 downto 11) = flip_id else '0';
i_add_sub <= instruction(12);
i_carry_nocarry <= instruction(11);
@ -674,7 +674,7 @@ begin
ALU_result(i) <= (shift_and_rotate_result(i) and i_shift_rotate)
or (in_port(i) and i_input)
or (arithmetic_result(i) and i_arithmetic)
-- or (flip_result(i) and i_flip) -- added new instruction
or (flip_result(i) and i_flip) -- added new instruction
or (logical_result(i) and i_logical);
end generate ALU_loop;

34
picoblaze.xise

@ -16,12 +16,12 @@
<files>
<file xil_pn:name="arithmatic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="carry_flag_logic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="interrupt_capture.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
@ -40,8 +40,8 @@
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="picoblaze.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="program_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
@ -76,29 +76,33 @@
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="toplevel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="projectVGA.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="controllerVGA.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="tb_vga1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="44"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="44"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="fontROM.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="programa_helloworld_int.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="flip.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
</files>

6
register_and_flag_enable.vhd

@ -18,7 +18,7 @@ entity register_and_flag_enable is
Port (i_logical: in std_logic;
i_arithmetic: in std_logic;
i_shift_rotate: in std_logic;
-- i_flip: in std_logic; -- added new instruction
i_flip: in std_logic; -- added new instruction
i_returni: in std_logic;
i_input: in std_logic;
active_interrupt : in std_logic;
@ -45,10 +45,10 @@ begin
--
-- added new instruction, uncomment this instruction and comment next instruction
-- to enable the new instruction
-- reg_instruction_decode <= (i_logical or i_arithmetic or i_shift_rotate or i_input or i_flip)
reg_instruction_decode <= (i_logical or i_arithmetic or i_shift_rotate or i_input or i_flip)
-- and (not active_interrupt);
reg_instruction_decode <= (i_logical or i_arithmetic or i_shift_rotate or i_input)
-- reg_instruction_decode <= (i_logical or i_arithmetic or i_shift_rotate or i_input)
and (not active_interrupt);
reg_pipeline_bit:

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