Browse Source

.gitignore fix

master
Enrique Fernandez 3 years ago
parent
commit
19fafab537
  1. 116
      IO_strobe_logic.vhd
  2. 128
      T_state_and_Reset.vhd
  3. 334
      arithmatic.vhd
  4. 2050
      assembly/asm.cpp
  5. 306
      assembly/programa_helloworld_int.asm
  6. 570
      assembly/programa_helloworld_int.vhd
  7. 104
      carry_flag_logic.vhd
  8. 66
      flip.vhd
  9. 120
      interrupt_capture.vhd
  10. 156
      interrupt_logic.vhd
  11. 128
      logical_bus_processing.vhd
  12. 1368
      picoblaze.vhd
  13. 146
      program_counter.vhd
  14. 570
      programa_helloworld.vhd
  15. 570
      programa_helloworld_int.vhd
  16. 182
      register_and_flag_enable.vhd
  17. 184
      register_bank.vhd
  18. 174
      shift_rotate.vhd
  19. 224
      stack_counter.vhd
  20. 208
      stack_ram.vhd
  21. 178
      tb.vhd
  22. BIN
      tb_vga1_isim_beh.wdb
  23. BIN
      tb_vga1_isim_beh1.wdb
  24. 632
      toplevel.vhd
  25. 347627
      write.txt
  26. 120
      zero_flag_logic.vhd

116
IO_strobe_logic.vhd

@ -1,58 +1,58 @@
--
-- Definition of the Input and Output Strobes
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity IO_strobe_logic is
Port (i_input : in std_logic;
i_output : in std_logic;
active_interrupt : in std_logic;
T_state : in std_logic;
reset : in std_logic;
write_strobe : out std_logic;
read_strobe : out std_logic;
clk : in std_logic);
end IO_strobe_logic;
--
architecture low_level_definition of IO_strobe_logic is
--
-- Internal signals
--
signal write_event : std_logic;
signal read_event : std_logic;
--
begin
--
write_event <= i_output and (not T_state) and (not active_interrupt);
write_flop:
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
write_strobe <= '0';
else write_strobe <= write_event;
end if;
end if;
end process write_flop;
read_event <= i_input and (not T_state) and (not active_interrupt);
read_flop:
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
read_strobe <= '0';
else read_strobe <= read_event;
end if;
end if;
end process read_flop;
--
end low_level_definition;
--
--
-- Definition of the Input and Output Strobes
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity IO_strobe_logic is
Port (i_input : in std_logic;
i_output : in std_logic;
active_interrupt : in std_logic;
T_state : in std_logic;
reset : in std_logic;
write_strobe : out std_logic;
read_strobe : out std_logic;
clk : in std_logic);
end IO_strobe_logic;
--
architecture low_level_definition of IO_strobe_logic is
--
-- Internal signals
--
signal write_event : std_logic;
signal read_event : std_logic;
--
begin
--
write_event <= i_output and (not T_state) and (not active_interrupt);
write_flop:
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
write_strobe <= '0';
else write_strobe <= write_event;
end if;
end if;
end process write_flop;
read_event <= i_input and (not T_state) and (not active_interrupt);
read_flop:
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
read_strobe <= '0';
else read_strobe <= read_event;
end if;
end if;
end process read_flop;
--
end low_level_definition;
--

128
T_state_and_Reset.vhd

@ -1,64 +1,64 @@
--
-- Definition of basic time T-state and clean reset
--
-- This function forms the basic 2 cycle T-state control used by the processor.
-- It also forms a clean synchronous reset pulse that is long enough to ensure
-- correct operation at start up and following a reset input.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity T_state_and_Reset is
Port ( reset_input : in std_logic;
internal_reset : out std_logic;
T_state : out std_logic;
clk : in std_logic);
end T_state_and_Reset;
--
architecture low_level_definition of T_state_and_Reset is
--
-- Internal signals
--
signal reset_delay1 : std_logic;
signal reset_delay2 : std_logic;
signal not_T_state : std_logic;
signal internal_T_state : std_logic;
--
begin
--
delay_flop1:
process (clk)
begin
if clk'event and clk = '1' then
reset_delay1 <= reset_input;
end if;
end process delay_flop1;
delay_flop2:
process (clk)
begin
if clk'event and clk = '1' then
reset_delay2 <= reset_delay1 or reset_input;
end if;
end process delay_flop2;
not_T_state <= not internal_T_state;
toggle_flop:
process (clk)
begin
if clk'event and clk = '1' then
if (reset_delay2 = '1') then
internal_T_state <= '0';
else internal_T_state <= not_T_state;
end if;
end if;
end process toggle_flop;
T_state <= internal_T_state;
internal_reset <= reset_delay2;
--
end low_level_definition;
--
--
-- Definition of basic time T-state and clean reset
--
-- This function forms the basic 2 cycle T-state control used by the processor.
-- It also forms a clean synchronous reset pulse that is long enough to ensure
-- correct operation at start up and following a reset input.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity T_state_and_Reset is
Port ( reset_input : in std_logic;
internal_reset : out std_logic;
T_state : out std_logic;
clk : in std_logic);
end T_state_and_Reset;
--
architecture low_level_definition of T_state_and_Reset is
--
-- Internal signals
--
signal reset_delay1 : std_logic;
signal reset_delay2 : std_logic;
signal not_T_state : std_logic;
signal internal_T_state : std_logic;
--
begin
--
delay_flop1:
process (clk)
begin
if clk'event and clk = '1' then
reset_delay1 <= reset_input;
end if;
end process delay_flop1;
delay_flop2:
process (clk)
begin
if clk'event and clk = '1' then
reset_delay2 <= reset_delay1 or reset_input;
end if;
end process delay_flop2;
not_T_state <= not internal_T_state;
toggle_flop:
process (clk)
begin
if clk'event and clk = '1' then
if (reset_delay2 = '1') then
internal_T_state <= '0';
else internal_T_state <= not_T_state;
end if;
end if;
end process toggle_flop;
T_state <= internal_T_state;
internal_reset <= reset_delay2;
--
end low_level_definition;
--

334
arithmatic.vhd

@ -1,167 +1,167 @@
--
-- Definition of an 8-bit arithmetic process
--
-- Operation
--
-- Two input operands are added or subtracted.
-- An input carry bit can be included in the calculation.
-- An output carry is always generated.
-- Carry signals work in the positive sense at all times.
--
-- code1 code0 Bit injected
--
-- 0 0 ADD
-- 0 1 ADD with carry
-- 1 0 SUB
-- 1 1 SUB with carry
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity arithmetic_process is
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end arithmetic_process;
--
architecture low_level_definition of arithmetic_process is
--
-- An 8-bit adder/subtractor
--
component addsub8
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
subtract : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end component;
--
-- Internal signals
--
signal carry_in_bit : std_logic;
signal carry_out_bit : std_logic;
signal modified_carry_out : std_logic;
--
begin
--
-- Selection of the carry input to add/sub
--
carry_in_bit <= (code1 and (not code0) and (not carry_in))
or (code1 and code0 and (not carry_in))
or (code1 and (not code0) and carry_in)
or ((not code1) and code0 and carry_in);
--
-- Main add/sub
--
add_sub_module: addsub8
port map ( first_operand => first_operand,
second_operand => second_operand,
carry_in => carry_in_bit,
subtract => code1,
Y => Y,
carry_out => carry_out_bit,
clk => clk);
--
-- Modification to carry output and pipeline
--
modified_carry_out <= code1 xor carry_out_bit;
pipeline_bit:
process (clk)
begin
if clk'event and clk = '1' then
carry_out <= modified_carry_out;
end if;
end
process pipeline_bit;
--
end low_level_definition;
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit adder/subtractor
--
-- subtract Operation
--
-- 0 ADD Y <= first_operand + second_operand
-- 1 SUB Y <= first_operand - second_operand
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity addsub8 is
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
subtract : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end addsub8;
--
architecture low_level_definition of addsub8 is
--
-- Internal signals
--
signal half_addsub : std_logic_vector(7 downto 0);
signal full_addsub : std_logic_vector(7 downto 0);
signal carry_chain : std_logic_vector(6 downto 0);
--
begin
bus_width_loop: for i in 0 to 7 generate
begin
lsb_carry: if i=0 generate
begin
carry_chain(i) <= carry_in when half_addsub(i)= '1' else first_operand(i);
full_addsub(i) <= half_addsub(i) xor carry_in;
end generate lsb_carry;
mid_carry: if i>0 and i<7 generate
begin
carry_chain(i) <= carry_chain(i-1) when half_addsub(i)= '1' else first_operand(i);
full_addsub(i) <= half_addsub(i) xor carry_chain(i-1);
end generate mid_carry;
msb_carry: if i=7 generate
begin
carry_out <= carry_chain(i-1) when half_addsub(i)= '1' else first_operand(i);
full_addsub(i) <= half_addsub(i) xor carry_chain(i-1);
end generate msb_carry;
half_addsub(i) <= (subtract and second_operand(i) and first_operand(i))
or (subtract and (not second_operand(i)) and (not first_operand(i)))
or ((not subtract) and (not second_operand(i)) and first_operand(i))
or ((not subtract) and second_operand(i) and (not first_operand(i)));
pipeline_bit:
process (clk)
begin
if clk'event and clk = '1' then
Y(i) <= full_addsub(i);
end if;
end
process pipeline_bit;
end generate bus_width_loop;
--
end low_level_definition;
--
-- Definition of an 8-bit arithmetic process
--
-- Operation
--
-- Two input operands are added or subtracted.
-- An input carry bit can be included in the calculation.
-- An output carry is always generated.
-- Carry signals work in the positive sense at all times.
--
-- code1 code0 Bit injected
--
-- 0 0 ADD
-- 0 1 ADD with carry
-- 1 0 SUB
-- 1 1 SUB with carry
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity arithmetic_process is
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end arithmetic_process;
--
architecture low_level_definition of arithmetic_process is
--
-- An 8-bit adder/subtractor
--
component addsub8
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
subtract : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end component;
--
-- Internal signals
--
signal carry_in_bit : std_logic;
signal carry_out_bit : std_logic;
signal modified_carry_out : std_logic;
--
begin
--
-- Selection of the carry input to add/sub
--
carry_in_bit <= (code1 and (not code0) and (not carry_in))
or (code1 and code0 and (not carry_in))
or (code1 and (not code0) and carry_in)
or ((not code1) and code0 and carry_in);
--
-- Main add/sub
--
add_sub_module: addsub8
port map ( first_operand => first_operand,
second_operand => second_operand,
carry_in => carry_in_bit,
subtract => code1,
Y => Y,
carry_out => carry_out_bit,
clk => clk);
--
-- Modification to carry output and pipeline
--
modified_carry_out <= code1 xor carry_out_bit;
pipeline_bit:
process (clk)
begin
if clk'event and clk = '1' then
carry_out <= modified_carry_out;
end if;
end
process pipeline_bit;
--
end low_level_definition;
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit adder/subtractor
--
-- subtract Operation
--
-- 0 ADD Y <= first_operand + second_operand
-- 1 SUB Y <= first_operand - second_operand
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity addsub8 is
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
subtract : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end addsub8;
--
architecture low_level_definition of addsub8 is
--
-- Internal signals
--
signal half_addsub : std_logic_vector(7 downto 0);
signal full_addsub : std_logic_vector(7 downto 0);
signal carry_chain : std_logic_vector(6 downto 0);
--
begin
bus_width_loop: for i in 0 to 7 generate
begin
lsb_carry: if i=0 generate
begin
carry_chain(i) <= carry_in when half_addsub(i)= '1' else first_operand(i);
full_addsub(i) <= half_addsub(i) xor carry_in;
end generate lsb_carry;
mid_carry: if i>0 and i<7 generate
begin
carry_chain(i) <= carry_chain(i-1) when half_addsub(i)= '1' else first_operand(i);
full_addsub(i) <= half_addsub(i) xor carry_chain(i-1);
end generate mid_carry;
msb_carry: if i=7 generate
begin
carry_out <= carry_chain(i-1) when half_addsub(i)= '1' else first_operand(i);
full_addsub(i) <= half_addsub(i) xor carry_chain(i-1);
end generate msb_carry;
half_addsub(i) <= (subtract and second_operand(i) and first_operand(i))
or (subtract and (not second_operand(i)) and (not first_operand(i)))
or ((not subtract) and (not second_operand(i)) and first_operand(i))
or ((not subtract) and second_operand(i) and (not first_operand(i)));
pipeline_bit:
process (clk)
begin
if clk'event and clk = '1' then
Y(i) <= full_addsub(i);
end if;
end
process pipeline_bit;
end generate bus_width_loop;
--
end low_level_definition;

2050
assembly/asm.cpp

File diff suppressed because it is too large

306
assembly/programa_helloworld_int.asm

@ -1,153 +1,153 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
;Transmision RS-232 por software.
;115200bps, 8 data bits, no parity, 1 stop bit, no flow control,
;part1: transmite por el puerte serie el contenido de la memoria RAM (64 bytes,portid[0-63])
;part2: genera numeros pseudo-aleatorios, bucle contador+interrupcion para transmitir numero.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;declaracion de constantes y variables
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
CONSTANT vga, FE
CONSTANT rs232, FF ; puerto comunicacion serie es el FF
; rx es el bit 0 del puerto FF(entrada)
; tx es el bit 7 del puerto FF(salida), esto es porque
;el hyperterminal envia primero el LSB, por eso vamos desplazando a la
;izquierda al recibir, y al enviar tambien, con lo que enviamos de nuevo
;el LSB primero como corresponde para que lo entienda el hyperterminal
NAMEREG s1, txreg ;buffer de transmision
NAMEREG s2, rxreg ;buffer de recepcion
NAMEREG s3, contbit ;contador de los 8 bits de datos
NAMEREG s4, cont1 ;contador de retardo1
NAMEREG s5, cont2 ;contador de retardo2
;
ADDRESS 00 ;el programa se cargara a partir de la dir 00
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;Inicio del programa
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DISABLE INTERRUPT
start: CALL recibe
;Instrucciones para la parte1
LOAD S7,00
parte1: INPUT txreg,S7
ADD txreg,00
JUMP Z parte2
CALL transmite
ADD S7,01
JUMP parte1
;Instrucciones para la parte2
parte2: ENABLE INTERRUPT
bucle1: LOAD S6,09
bucle2: SUB S6,01
JUMP NZ bucle2
LOAD S6,09
JUMP bucle2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;Rutina de recepcion de caracteres
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
recibe: ;esperamos a que se reciba un bit de inicio
INPUT rxreg, rs232
AND rxreg, 80
JUMP NZ, recibe
CALL wait_05bit
;almacenamos los 8 bits de datos
LOAD contbit,09
next_rx_bit: CALL wait_1bit
SR0 rxreg
INPUT s0, rs232
AND s0, 80
OR rxreg, s0
SUB contbit, 01
JUMP NZ, next_rx_bit
RETURN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;Rutina de transmision de caracteres
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
transmite: ;enviamos un bit de inicio
LOAD s0, 00
OUTPUT s0, rs232
CALL wait_1bit
;enviamos los 8 bits de datos
LOAD contbit, 08
next_tx_bit: OUTPUT txreg, rs232
CALL wait_1bit
SR0 txreg
SUB contbit, 01
JUMP NZ, next_tx_bit
;enviamos un bit de parada
LOAD s0, FF
OUTPUT s0, rs232
CALL wait_1bit
RETURN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;Rutina espera 1 bit (a 9600bps)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;clk=50MHz, 9600bps, cont1=0A, cont2=80
;esta rutina ejecuta 1 + (1 + 10*(1 + 128*2 + 2)) + 1 = 2593 instruciones,
;aproximandose al numero teorico de (104,16us/bit)/(0,04 us/instruc) = 2604,166 instr/bit necesarias.
;clk=40MHz, 57600bps, cont1=05, cont2=21
;esta rutina ejecuta 1 + (1 + 5*(1 + 33*2 + 2)) + 1 = instruciones,
;aproximandose al numero teorico de (17,36us/bit)/(0,05 us/instruc) = 347,2 instr/bit necesarias.
;clk=50MHz, 115200bps, cont1=03, cont2=22
;esta rutina ejecuta 1 + (1 + 3*(1 + 34*2 + 2)) + 1 = 216 instruciones,
;aproximandose al numero teorico de (8,68us/bit)/(0,04 us/instruc) = 217 instr/bit necesarias.
;clk=50MHz, 230400bps, cont1= 03, cont2= 10
;esta rutina ejecuta 1 + (1 + 3*(1 + 16*2 + 2)) + 1 = 108 instruciones,
;aproximandose al numero teorico de (4,34us/bit)/(0,04 us/instruc) = 108,5 instr/bit necesarias.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;OJO: con el USB2COM no he conseguido pasar de los 230400bps bien.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;clk=50MHz, 460800bps, cont1= 03, cont2=06 OJO:Hay que ponerle 1 menos a cont2 y que tome
;caracteres ascii de 7 bits para que funcione.
;esta rutina ejecuta 1 + (1 + 3*(1 + 7*2 + 2)) + 1 = 54 instruciones,
;aproximandose al numero teorico de (2,17us/bit)/(0,04 us/instruc) = 54,25 instr/bit necesarias.
;clk=50MHz, 921600bps, cont1=01, cont2=0A NO FUNCIONA
;esta rutina ejecuta 1 + (1 + 1*(1 + 10*2 + 2)) + 1 = 26 instruciones,
;aproximandose al numero teorico de (1,085us/bit)/(0,04 us/instruc) = 27,127 instr/bit necesarias.
wait_1bit: LOAD cont1, 03
espera2: LOAD cont2, 22
espera1: SUB cont2, 01
JUMP NZ, espera1
SUB cont1, 01
JUMP NZ, espera2
RETURN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;Rutina espera 0,5 bits (bit de inicio, a 9600bps)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;clk=50MHz, 9600bps, cont1=05, cont2=80
;1 + (1 + 5*(1 + 128*2 + 2)) + 1 = 1298; aprox = 1302
;clk=40MHz, 57600bps, cont1=03, cont2=1B
;1 + (1 + 3*(1 + 27*2 + 2)) + 1 = 1298; aprox = 173.6
;clk=50MHz, 115200bps, cont1=03, cont2=10
;1 + (1 + 3*(1 + 16*2 + 2)) + 1 = 108; aprox = 108.5
;clk=50MHz, 230400bps, cont1= 03, cont2= 07
;1 + (1 + 3*(1 + 7*2 + 2)) + 1 = 54; aprox = 54,25
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;OJO: con el USB2COM no he conseguido pasar de los 230400bps bien.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;clk=50MHz, 460800bps, cont1= 01, cont2= 0A
;1 + (1 + 1*(1 + 10*2 + 2)) + 1 = 26; aprox = 27,125
;clk=50MHz, 921600bps, cont1=01, cont2=04 NO FUNCIONA
;1 + (1 + 1*(1 + 4*2 + 2)) + 1 = 14; aprox = 13,56
wait_05bit: LOAD cont1, 03
espera4: LOAD cont2, 10
espera3: SUB cont2, 01
JUMP NZ, espera3
SUB cont1, 01
JUMP NZ, espera4
RETURN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; FIN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; RUTINA DE ATENCION A LA INTERRUPCION
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
interrup: DISABLE INTERRUPT
CALL recibe
LOAD txreg,rxreg
OUTPUT txreg, vga ; Mandamos el valor del teclado al VGA
CALL transmite ; echo rs232?
RETURNI ENABLE
ADDRESS FF
JUMP interrup
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
;Transmision RS-232 por software.
;115200bps, 8 data bits, no parity, 1 stop bit, no flow control,
;part1: transmite por el puerte serie el contenido de la memoria RAM (64 bytes,portid[0-63])
;part2: genera numeros pseudo-aleatorios, bucle contador+interrupcion para transmitir numero.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;declaracion de constantes y variables
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
CONSTANT vga, FE
CONSTANT rs232, FF ; puerto comunicacion serie es el FF
; rx es el bit 0 del puerto FF(entrada)
; tx es el bit 7 del puerto FF(salida), esto es porque
;el hyperterminal envia primero el LSB, por eso vamos desplazando a la
;izquierda al recibir, y al enviar tambien, con lo que enviamos de nuevo
;el LSB primero como corresponde para que lo entienda el hyperterminal
NAMEREG s1, txreg ;buffer de transmision
NAMEREG s2, rxreg ;buffer de recepcion
NAMEREG s3, contbit ;contador de los 8 bits de datos
NAMEREG s4, cont1 ;contador de retardo1
NAMEREG s5, cont2 ;contador de retardo2
;
ADDRESS 00 ;el programa se cargara a partir de la dir 00
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;Inicio del programa
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DISABLE INTERRUPT
start: CALL recibe
;Instrucciones para la parte1
LOAD S7,00
parte1: INPUT txreg,S7
ADD txreg,00
JUMP Z parte2
CALL transmite
ADD S7,01
JUMP parte1
;Instrucciones para la parte2
parte2: ENABLE INTERRUPT
bucle1: LOAD S6,09
bucle2: SUB S6,01
JUMP NZ bucle2
LOAD S6,09
JUMP bucle2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;Rutina de recepcion de caracteres
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
recibe: ;esperamos a que se reciba un bit de inicio
INPUT rxreg, rs232
AND rxreg, 80
JUMP NZ, recibe
CALL wait_05bit
;almacenamos los 8 bits de datos
LOAD contbit,09
next_rx_bit: CALL wait_1bit
SR0 rxreg
INPUT s0, rs232
AND s0, 80
OR rxreg, s0
SUB contbit, 01
JUMP NZ, next_rx_bit
RETURN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;Rutina de transmision de caracteres
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
transmite: ;enviamos un bit de inicio
LOAD s0, 00
OUTPUT s0, rs232
CALL wait_1bit
;enviamos los 8 bits de datos
LOAD contbit, 08
next_tx_bit: OUTPUT txreg, rs232
CALL wait_1bit
SR0 txreg
SUB contbit, 01
JUMP NZ, next_tx_bit
;enviamos un bit de parada
LOAD s0, FF
OUTPUT s0, rs232
CALL wait_1bit
RETURN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;Rutina espera 1 bit (a 9600bps)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;clk=50MHz, 9600bps, cont1=0A, cont2=80
;esta rutina ejecuta 1 + (1 + 10*(1 + 128*2 + 2)) + 1 = 2593 instruciones,
;aproximandose al numero teorico de (104,16us/bit)/(0,04 us/instruc) = 2604,166 instr/bit necesarias.
;clk=40MHz, 57600bps, cont1=05, cont2=21
;esta rutina ejecuta 1 + (1 + 5*(1 + 33*2 + 2)) + 1 = instruciones,
;aproximandose al numero teorico de (17,36us/bit)/(0,05 us/instruc) = 347,2 instr/bit necesarias.
;clk=50MHz, 115200bps, cont1=03, cont2=22
;esta rutina ejecuta 1 + (1 + 3*(1 + 34*2 + 2)) + 1 = 216 instruciones,
;aproximandose al numero teorico de (8,68us/bit)/(0,04 us/instruc) = 217 instr/bit necesarias.
;clk=50MHz, 230400bps, cont1= 03, cont2= 10
;esta rutina ejecuta 1 + (1 + 3*(1 + 16*2 + 2)) + 1 = 108 instruciones,
;aproximandose al numero teorico de (4,34us/bit)/(0,04 us/instruc) = 108,5 instr/bit necesarias.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;OJO: con el USB2COM no he conseguido pasar de los 230400bps bien.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;clk=50MHz, 460800bps, cont1= 03, cont2=06 OJO:Hay que ponerle 1 menos a cont2 y que tome
;caracteres ascii de 7 bits para que funcione.
;esta rutina ejecuta 1 + (1 + 3*(1 + 7*2 + 2)) + 1 = 54 instruciones,
;aproximandose al numero teorico de (2,17us/bit)/(0,04 us/instruc) = 54,25 instr/bit necesarias.
;clk=50MHz, 921600bps, cont1=01, cont2=0A NO FUNCIONA
;esta rutina ejecuta 1 + (1 + 1*(1 + 10*2 + 2)) + 1 = 26 instruciones,
;aproximandose al numero teorico de (1,085us/bit)/(0,04 us/instruc) = 27,127 instr/bit necesarias.
wait_1bit: LOAD cont1, 03
espera2: LOAD cont2, 22
espera1: SUB cont2, 01
JUMP NZ, espera1
SUB cont1, 01
JUMP NZ, espera2
RETURN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;Rutina espera 0,5 bits (bit de inicio, a 9600bps)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;clk=50MHz, 9600bps, cont1=05, cont2=80
;1 + (1 + 5*(1 + 128*2 + 2)) + 1 = 1298; aprox = 1302
;clk=40MHz, 57600bps, cont1=03, cont2=1B
;1 + (1 + 3*(1 + 27*2 + 2)) + 1 = 1298; aprox = 173.6
;clk=50MHz, 115200bps, cont1=03, cont2=10
;1 + (1 + 3*(1 + 16*2 + 2)) + 1 = 108; aprox = 108.5
;clk=50MHz, 230400bps, cont1= 03, cont2= 07
;1 + (1 + 3*(1 + 7*2 + 2)) + 1 = 54; aprox = 54,25
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;OJO: con el USB2COM no he conseguido pasar de los 230400bps bien.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;clk=50MHz, 460800bps, cont1= 01, cont2= 0A
;1 + (1 + 1*(1 + 10*2 + 2)) + 1 = 26; aprox = 27,125
;clk=50MHz, 921600bps, cont1=01, cont2=04 NO FUNCIONA
;1 + (1 + 1*(1 + 4*2 + 2)) + 1 = 14; aprox = 13,56
wait_05bit: LOAD cont1, 03
espera4: LOAD cont2, 10
espera3: SUB cont2, 01
JUMP NZ, espera3
SUB cont1, 01
JUMP NZ, espera4
RETURN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; FIN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; RUTINA DE ATENCION A LA INTERRUPCION
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
interrup: DISABLE INTERRUPT
CALL recibe
LOAD txreg,rxreg
OUTPUT txreg, vga ; Mandamos el valor del teclado al VGA
CALL transmite ; echo rs232?
RETURNI ENABLE
ADDRESS FF
JUMP interrup

570
assembly/programa_helloworld_int.vhd

@ -1,285 +1,285 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity programa_helloworld_int is
port( address : in std_logic_vector(7 downto 0);
clk : in std_logic;
dout : out std_logic_vector(15 downto 0));
end;
architecture v1 of programa_helloworld_int is
constant ROM_WIDTH: INTEGER:= 16;
constant ROM_LENGTH: INTEGER:= 256;
subtype rom_word is std_logic_vector(ROM_WIDTH-1 downto 0);
type rom_table is array (0 to ROM_LENGTH-1) of rom_word;
constant rom: rom_table := rom_table'(
"1111000000000000",
"1101100000001111",
"0000011100000000",
"1100000111100000",
"0010000100000000",
"1101010000001001",
"1101100000011100",
"0010011100000001",
"1101000000000011",
"1111000000000001",
"0000011000001001",
"0011011000000001",
"1101010100001011",
"0000011000001001",
"1101000000001011",
"1000001011111111",
"0000101010000000",
"1101010100001111",
"1101100000110000",
"0000001100001001",
"1101100000101001",
"1010001000001110",
"1000000011111111",
"0000100010000000",
"0101001000000000",
"0011001100000001",
"1101010100010100",
"1001000000000000",
"0000000000000000",
"1000100011111111",
"1101100000101001",
"0000001100001000",
"1000100111111111",
"1101100000101001",
"1010000100001110",
"0011001100000001",
"1101010100100000",
"0000000011111111",
"1000100011111111",
"1101100000101001",
"1001000000000000",
"0000010000000011",
"0000010100100010",
"0011010100000001",
"1101010100101011",
"0011010000000001",
"1101010100101010",
"1001000000000000",
"0000010000000011",
"0000010100010000",
"0011010100000001",
"1101010100110010",
"0011010000000001",
"1101010100110001",
"1001000000000000",
"1111000000000000",
"1101100000001111",
"0100000101000000",
"1101100000011100",
"0010011000110000",
"0100000111000000",
"1101100000011100",
"1011000000000001",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"1101000000110111");
begin
process (clk)
begin
if clk'event and clk = '1' then
dout <= rom(conv_integer(address));
end if;
end process;
end v1;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity programa_helloworld_int is
port( address : in std_logic_vector(7 downto 0);
clk : in std_logic;
dout : out std_logic_vector(15 downto 0));
end;
architecture v1 of programa_helloworld_int is
constant ROM_WIDTH: INTEGER:= 16;
constant ROM_LENGTH: INTEGER:= 256;
subtype rom_word is std_logic_vector(ROM_WIDTH-1 downto 0);
type rom_table is array (0 to ROM_LENGTH-1) of rom_word;
constant rom: rom_table := rom_table'(
"1111000000000000",
"1101100000001111",
"0000011100000000",
"1100000111100000",
"0010000100000000",
"1101010000001001",
"1101100000011100",
"0010011100000001",
"1101000000000011",
"1111000000000001",
"0000011000001001",
"0011011000000001",
"1101010100001011",
"0000011000001001",
"1101000000001011",
"1000001011111111",
"0000101010000000",
"1101010100001111",
"1101100000110000",
"0000001100001001",
"1101100000101001",
"1010001000001110",
"1000000011111111",
"0000100010000000",
"0101001000000000",
"0011001100000001",
"1101010100010100",
"1001000000000000",
"0000000000000000",
"1000100011111111",
"1101100000101001",
"0000001100001000",
"1000100111111111",
"1101100000101001",
"1010000100001110",
"0011001100000001",
"1101010100100000",
"0000000011111111",
"1000100011111111",
"1101100000101001",
"1001000000000000",
"0000010000000011",
"0000010100100010",
"0011010100000001",
"1101010100101011",
"0011010000000001",
"1101010100101010",
"1001000000000000",
"0000010000000011",
"0000010100010000",
"0011010100000001",
"1101010100110010",
"0011010000000001",
"1101010100110001",
"1001000000000000",
"1111000000000000",
"1101100000001111",
"0100000101000000",
"1101100000011100",
"0010011000110000",
"0100000111000000",
"1101100000011100",
"1011000000000001",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"1101000000110111");
begin
process (clk)
begin
if clk'event and clk = '1' then
dout <= rom(conv_integer(address));
end if;
end process;
end v1;

104
carry_flag_logic.vhd

@ -1,52 +1,52 @@
--
-- Definition of the Carry Flag
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity carry_flag_logic is
Port (add_sub : in std_logic;
shift : in std_logic;
returni : in std_logic;
shift_carry : in std_logic;
add_sub_carry : in std_logic;
shadow_carry : in std_logic;
reset : in std_logic;
flag_enable : in std_logic;
carry_flag : out std_logic;
clk : in std_logic);
end carry_flag_logic;
--
architecture low_level_definition of carry_flag_logic is
--
-- Internal signals
--
signal carry_status : std_logic;
signal next_carry_flag : std_logic;
--
begin
--
carry_status <= (shift_carry and shift) or (add_sub_carry and add_sub);
--
-- Select new carry status or the shaddow flag for a RETURNI
--
next_carry_flag <= (shadow_carry and returni) or (shadow_carry and carry_status) or
(carry_status and (shift or add_sub));
carry_flag_flop:
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
carry_flag <= '0';
else if flag_enable = '1' then
carry_flag <= next_carry_flag;
end if;
end if;
end if;
end process carry_flag_flop;
--
end low_level_definition;
--
--
-- Definition of the Carry Flag
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity carry_flag_logic is
Port (add_sub : in std_logic;
shift : in std_logic;
returni : in std_logic;
shift_carry : in std_logic;
add_sub_carry : in std_logic;
shadow_carry : in std_logic;
reset : in std_logic;
flag_enable : in std_logic;
carry_flag : out std_logic;
clk : in std_logic);
end carry_flag_logic;
--
architecture low_level_definition of carry_flag_logic is
--
-- Internal signals
--
signal carry_status : std_logic;
signal next_carry_flag : std_logic;
--
begin
--
carry_status <= (shift_carry and shift) or (add_sub_carry and add_sub);
--
-- Select new carry status or the shaddow flag for a RETURNI
--
next_carry_flag <= (shadow_carry and returni) or (shadow_carry and carry_status) or
(carry_status and (shift or add_sub));
carry_flag_flop:
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
carry_flag <= '0';
else if flag_enable = '1' then
carry_flag <= next_carry_flag;
end if;
end if;
end if;
end process carry_flag_flop;
--
end low_level_definition;
--

66
flip.vhd

@ -1,33 +1,33 @@
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit flip process
-- Operation
--
-- The input operand is flipped
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity flip is
Port (operand : in std_logic_vector(7 downto 0);
Y : out std_logic_vector(7 downto 0);
clk : in std_logic);
end flip;
--
architecture low_level_definition of flip is
begin
bus_width_loop: for i in 0 to 7 generate
begin
FF:
process (clk)
begin
if (clk'event and clk = '1') then
Y(i) <= operand(7-i);
end if;
end process FF;
end generate bus_width_loop;
--
end low_level_definition;
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit flip process
-- Operation
--
-- The input operand is flipped
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity flip is
Port (operand : in std_logic_vector(7 downto 0);
Y : out std_logic_vector(7 downto 0);
clk : in std_logic);
end flip;
--
architecture low_level_definition of flip is
begin
bus_width_loop: for i in 0 to 7 generate
begin
FF:
process (clk)
begin
if (clk'event and clk = '1') then
Y(i) <= operand(7-i);
end if;
end process FF;
end generate bus_width_loop;
--
end low_level_definition;

120
interrupt_capture.vhd

@ -1,60 +1,60 @@
--
-- Definition of interrupt signal capture
--
-- This function accepts the external interrupt signal and synchronises it to the
-- processor logic. It then forms a single cycle pulse provided that interrupts
-- are currently enabled.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity interrupt_capture is
Port (interrupt : in std_logic;
T_state : in std_logic;
reset : in std_logic;
interrupt_enable : in std_logic;
active_interrupt : out std_logic;
clk : in std_logic);
end interrupt_capture;
--
architecture low_level_definition of interrupt_capture is
--
-- Internal signals
--
signal clean_interrupt : std_logic;
signal interrupt_pulse : std_logic;
signal active_interrupt_pulse : std_logic;
--
begin
input_flop:
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
clean_interrupt <= '0';
else clean_interrupt <= interrupt;
end if;
end if;
end process input_flop;
interrupt_pulse <= (not active_interrupt_pulse) and interrupt_enable and clean_interrupt and T_state;
toggle_flop:
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
active_interrupt_pulse <= '0';
else active_interrupt_pulse <= interrupt_pulse;
end if;
end if;
end process toggle_flop;
active_interrupt <= active_interrupt_pulse;
--
end low_level_definition;
--
--
-- Definition of interrupt signal capture
--
-- This function accepts the external interrupt signal and synchronises it to the
-- processor logic. It then forms a single cycle pulse provided that interrupts
-- are currently enabled.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity interrupt_capture is
Port (interrupt : in std_logic;
T_state : in std_logic;
reset : in std_logic;
interrupt_enable : in std