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all picoblaze files added

master
Raniita 3 years ago
parent
commit
079d167360
  1. 58
      IO_strobe_logic.vhd
  2. 73
      PicoBlaze_s3estarter.ucf
  3. 64
      T_state_and_Reset.vhd
  4. 167
      arithmatic.vhd
  5. 52
      carry_flag_logic.vhd
  6. 33
      flip.vhd
  7. 60
      interrupt_capture.vhd
  8. 78
      interrupt_logic.vhd
  9. 215
      iseconfig/picoblaze.xreport
  10. 64
      logical_bus_processing.vhd
  11. 28
      picoblaze.gise
  12. 684
      picoblaze.vhd
  13. 439
      picoblaze.xise
  14. 79
      picoblaze_summary.html
  15. 73
      program_counter.vhd
  16. 285
      programa_helloworld.vhd
  17. 91
      register_and_flag_enable.vhd
  18. 92
      register_bank.vhd
  19. 87
      shift_rotate.vhd
  20. 112
      stack_counter.vhd
  21. 104
      stack_ram.vhd
  22. 89
      tb.vhd
  23. 79
      tb_summary.html
  24. 112
      toplevel.vhd
  25. 79
      toplevel_summary.html
  26. 60
      zero_flag_logic.vhd

58
IO_strobe_logic.vhd

@ -0,0 +1,58 @@
--
-- Definition of the Input and Output Strobes
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity IO_strobe_logic is
Port (i_input : in std_logic;
i_output : in std_logic;
active_interrupt : in std_logic;
T_state : in std_logic;
reset : in std_logic;
write_strobe : out std_logic;
read_strobe : out std_logic;
clk : in std_logic);
end IO_strobe_logic;
--
architecture low_level_definition of IO_strobe_logic is
--
-- Internal signals
--
signal write_event : std_logic;
signal read_event : std_logic;
--
begin
--
write_event <= i_output and (not T_state) and (not active_interrupt);
write_flop:
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
write_strobe <= '0';
else write_strobe <= write_event;
end if;
end if;
end process write_flop;
read_event <= i_input and (not T_state) and (not active_interrupt);
read_flop:
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
read_strobe <= '0';
else read_strobe <= read_event;
end if;
end if;
end process read_flop;
--
end low_level_definition;
--

73
PicoBlaze_s3estarter.ucf

@ -0,0 +1,73 @@
# ==== Clock inputs (CLK) ====
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
NET "clk" PERIOD = 20.0ns HIGH 40%;
# ==== Slide Switches (SW) ====
#NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
#NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
#NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
#NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
# ==== Discrete LEDs (LED) ====
# These are shared connections with the FX2 connector
NET "LED" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
## ==== RS-232 Serial Ports (RS232) ====
NET "rx" LOC = "R7" | IOSTANDARD = LVTTL ;
NET "tx" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
#NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ;
#NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
#NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
#NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
#
## ==== Rotary Pushbutton Switch (ROT) ====
#NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
#NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
#NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
#
## ==== Pushbuttons (BTN) ====
#NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
#NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "reset" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
#NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
#NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
#
#NET "in_port<7>" LOC = "";
#NET "in_port<6>" LOC = "";
#NET "in_port<5>" LOC = "";
#NET "in_port<4>" LOC = "";
#NET "in_port<3>" LOC = "";
#NET "in_port<2>" LOC = "";
#NET "in_port<1>" LOC = "";
#NET "in_port<0>" LOC = "";
#NET "out_port<7>" LOC = "";
#NET "out_port<6>" LOC = "";
#NET "out_port<5>" LOC = "";
#NET "out_port<4>" LOC = "";
#NET "out_port<3>" LOC = "";
#NET "out_port<2>" LOC = "";
#NET "out_port<1>" LOC = "";
#NET "out_port<0>" LOC = "";
#NET "port_id<7>" LOC = "";
#NET "port_id<6>" LOC = "";
#NET "port_id<5>" LOC = "";
#NET "port_id<4>" LOC = "";
#NET "port_id<3>" LOC = "";
#NET "port_id<2>" LOC = "";
#NET "port_id<1>" LOC = "";
#NET "port_id<0>" LOC = "";
#NET "a5" LOC = "";
#NET "read_strobe" LOC = "";
#NET "write_strobe" LOC = "";
#NET "interrupt" LOC = "";

64
T_state_and_Reset.vhd

@ -0,0 +1,64 @@
--
-- Definition of basic time T-state and clean reset
--
-- This function forms the basic 2 cycle T-state control used by the processor.
-- It also forms a clean synchronous reset pulse that is long enough to ensure
-- correct operation at start up and following a reset input.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity T_state_and_Reset is
Port ( reset_input : in std_logic;
internal_reset : out std_logic;
T_state : out std_logic;
clk : in std_logic);
end T_state_and_Reset;
--
architecture low_level_definition of T_state_and_Reset is
--
-- Internal signals
--
signal reset_delay1 : std_logic;
signal reset_delay2 : std_logic;
signal not_T_state : std_logic;
signal internal_T_state : std_logic;
--
begin
--
delay_flop1:
process (clk)
begin
if clk'event and clk = '1' then
reset_delay1 <= reset_input;
end if;
end process delay_flop1;
delay_flop2:
process (clk)
begin
if clk'event and clk = '1' then
reset_delay2 <= reset_delay1 or reset_input;
end if;
end process delay_flop2;
not_T_state <= not internal_T_state;
toggle_flop:
process (clk)
begin
if clk'event and clk = '1' then
if (reset_delay2 = '1') then
internal_T_state <= '0';
else internal_T_state <= not_T_state;
end if;
end if;
end process toggle_flop;
T_state <= internal_T_state;
internal_reset <= reset_delay2;
--
end low_level_definition;
--

167
arithmatic.vhd

@ -0,0 +1,167 @@
--
-- Definition of an 8-bit arithmetic process
--
-- Operation
--
-- Two input operands are added or subtracted.
-- An input carry bit can be included in the calculation.
-- An output carry is always generated.
-- Carry signals work in the positive sense at all times.
--
-- code1 code0 Bit injected
--
-- 0 0 ADD
-- 0 1 ADD with carry
-- 1 0 SUB
-- 1 1 SUB with carry
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity arithmetic_process is
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end arithmetic_process;
--
architecture low_level_definition of arithmetic_process is
--
-- An 8-bit adder/subtractor
--
component addsub8
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
subtract : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end component;
--
-- Internal signals
--
signal carry_in_bit : std_logic;
signal carry_out_bit : std_logic;
signal modified_carry_out : std_logic;
--
begin
--
-- Selection of the carry input to add/sub
--
carry_in_bit <= (code1 and (not code0) and (not carry_in))
or (code1 and code0 and (not carry_in))
or (code1 and (not code0) and carry_in)
or ((not code1) and code0 and carry_in);
--
-- Main add/sub
--
add_sub_module: addsub8
port map ( first_operand => first_operand,
second_operand => second_operand,
carry_in => carry_in_bit,
subtract => code1,
Y => Y,
carry_out => carry_out_bit,
clk => clk);
--
-- Modification to carry output and pipeline
--
modified_carry_out <= code1 xor carry_out_bit;
pipeline_bit:
process (clk)
begin
if clk'event and clk = '1' then
carry_out <= modified_carry_out;
end if;
end
process pipeline_bit;
--
end low_level_definition;
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit adder/subtractor
--
-- subtract Operation
--
-- 0 ADD Y <= first_operand + second_operand
-- 1 SUB Y <= first_operand - second_operand
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity addsub8 is
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
subtract : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end addsub8;
--
architecture low_level_definition of addsub8 is
--
-- Internal signals
--
signal half_addsub : std_logic_vector(7 downto 0);
signal full_addsub : std_logic_vector(7 downto 0);
signal carry_chain : std_logic_vector(6 downto 0);
--
begin
bus_width_loop: for i in 0 to 7 generate
begin
lsb_carry: if i=0 generate
begin
carry_chain(i) <= carry_in when half_addsub(i)= '1' else first_operand(i);
full_addsub(i) <= half_addsub(i) xor carry_in;
end generate lsb_carry;
mid_carry: if i>0 and i<7 generate
begin
carry_chain(i) <= carry_chain(i-1) when half_addsub(i)= '1' else first_operand(i);
full_addsub(i) <= half_addsub(i) xor carry_chain(i-1);
end generate mid_carry;
msb_carry: if i=7 generate
begin
carry_out <= carry_chain(i-1) when half_addsub(i)= '1' else first_operand(i);
full_addsub(i) <= half_addsub(i) xor carry_chain(i-1);
end generate msb_carry;
half_addsub(i) <= (subtract and second_operand(i) and first_operand(i))
or (subtract and (not second_operand(i)) and (not first_operand(i)))
or ((not subtract) and (not second_operand(i)) and first_operand(i))
or ((not subtract) and second_operand(i) and (not first_operand(i)));
pipeline_bit:
process (clk)
begin
if clk'event and clk = '1' then
Y(i) <= full_addsub(i);
end if;
end
process pipeline_bit;
end generate bus_width_loop;
--
end low_level_definition;

52
carry_flag_logic.vhd

@ -0,0 +1,52 @@
--
-- Definition of the Carry Flag
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity carry_flag_logic is
Port (add_sub : in std_logic;
shift : in std_logic;
returni : in std_logic;
shift_carry : in std_logic;
add_sub_carry : in std_logic;
shadow_carry : in std_logic;
reset : in std_logic;
flag_enable : in std_logic;
carry_flag : out std_logic;
clk : in std_logic);
end carry_flag_logic;
--
architecture low_level_definition of carry_flag_logic is
--
-- Internal signals
--
signal carry_status : std_logic;
signal next_carry_flag : std_logic;
--
begin
--
carry_status <= (shift_carry and shift) or (add_sub_carry and add_sub);
--
-- Select new carry status or the shaddow flag for a RETURNI
--
next_carry_flag <= (shadow_carry and returni) or (shadow_carry and carry_status) or
(carry_status and (shift or add_sub));
carry_flag_flop:
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
carry_flag <= '0';
else if flag_enable = '1' then
carry_flag <= next_carry_flag;
end if;
end if;
end if;
end process carry_flag_flop;
--
end low_level_definition;
--

33
flip.vhd

@ -0,0 +1,33 @@
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit flip process
-- Operation
--
-- The input operand is flipped
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity flip is
Port (operand : in std_logic_vector(7 downto 0);
Y : out std_logic_vector(7 downto 0);
clk : in std_logic);
end flip;
--
architecture low_level_definition of flip is
begin
bus_width_loop: for i in 0 to 7 generate
begin
FF:
process (clk)
begin
if (clk'event and clk = '1') then
Y(i) <= operand(7-i);
end if;
end process FF;
end generate bus_width_loop;
--
end low_level_definition;

60
interrupt_capture.vhd

@ -0,0 +1,60 @@
--
-- Definition of interrupt signal capture
--
-- This function accepts the external interrupt signal and synchronises it to the
-- processor logic. It then forms a single cycle pulse provided that interrupts
-- are currently enabled.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity interrupt_capture is
Port (interrupt : in std_logic;
T_state : in std_logic;
reset : in std_logic;
interrupt_enable : in std_logic;
active_interrupt : out std_logic;
clk : in std_logic);
end interrupt_capture;
--
architecture low_level_definition of interrupt_capture is
--
-- Internal signals
--
signal clean_interrupt : std_logic;
signal interrupt_pulse : std_logic;
signal active_interrupt_pulse : std_logic;
--
begin
input_flop:
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
clean_interrupt <= '0';
else clean_interrupt <= interrupt;
end if;
end if;
end process input_flop;
interrupt_pulse <= (not active_interrupt_pulse) and interrupt_enable and clean_interrupt and T_state;
toggle_flop:
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
active_interrupt_pulse <= '0';
else active_interrupt_pulse <= interrupt_pulse;
end if;
end if;
end process toggle_flop;
active_interrupt <= active_interrupt_pulse;
--
end low_level_definition;
--

78
interrupt_logic.vhd

@ -0,0 +1,78 @@
--
-- Definition of interrupt enable and shaddow flags
--
-- This function decodes the ENABLE and DSIABLE INTERRUPT instructions as well as
-- the RETURNI ENABLE and RETURNI DISABLE instructions to determine if future interrupts
-- will be enabled.
--
-- It also provideds the shaddow flags which store the flag status at time of an
-- interrupt.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity interrupt_logic is
Port (i_interrupt : in std_logic;
i_returni : in std_logic;
instruction0 : in std_logic;
active_interrupt : in std_logic;
carry_flag : in std_logic;
zero_flag : in std_logic;
reset : in std_logic;
interrupt_enable : out std_logic;
shaddow_carry : out std_logic;
shaddow_zero : out std_logic;
clk : in std_logic);
end interrupt_logic;
--
architecture low_level_definition of interrupt_logic is
--
-- Internal signals
--
signal update_enable : std_logic;
signal new_enable_value : std_logic;
--
begin
update_enable <= (i_interrupt and (not active_interrupt))
or active_interrupt or i_returni;
new_enable_value <= instruction0 and (not active_interrupt);
int_enable_flop:
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
interrupt_enable <= '0';
else if update_enable = '1' then
interrupt_enable <= new_enable_value;
end if;
end if;
end if;
end process int_enable_flop;
preserve_carry_flop:
process (clk)
begin
if clk'event and clk = '1' then
if active_interrupt = '1' then
shaddow_carry <= carry_flag;
end if;
end if;
end process preserve_carry_flop;
preserve_zero_flop:
process (clk)
begin
if clk'event and clk = '1' then
if active_interrupt = '1' then
shaddow_zero <= zero_flag;
end if;
end if;
end process preserve_zero_flop;
--
end low_level_definition;
--

215
iseconfig/picoblaze.xreport

@ -0,0 +1,215 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2019-03-13T20:32:04</DateModified>
<ModuleName>tb</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/rani/Desktop/git/picoblaze/iseconfig/picoblaze.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/rani/Desktop/git/picoblaze</ImplementationReportsDirectory>
<DateInitialized>2019-03-13T20:32:04</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="tb_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="tb_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="tb_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="tb_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="tb_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="tb.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="tb_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="tb_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="tb.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="tb_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="tb_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
</viewgroup>
<viewgroup label="XPS Reports" >
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="tb.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
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<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
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<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
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<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
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<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
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<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
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<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
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<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
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<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="tb.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="tb.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="tb.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
</view>
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/tb_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/tb_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="tb_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="tb_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="tb_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/tb_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="tb_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="tb_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="tb.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="tb_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="tb.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="tb.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="tb.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="tb.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="tb_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
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<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="tb_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="tb.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
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<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="tb.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
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<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="tb.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/tb_timesim.nlf" label="Post-Fit Simulation Model Report" />
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</report-views>

64
logical_bus_processing.vhd

@ -0,0 +1,64 @@
--
-- Definition of an 8-bit logical processing unit
--
-- This function provide the logical bit operations.
-- The function contains an output pipeline register using 8 FDs.
--
-- Code1 Code0 Bit Operation
--
-- 0 0 LOAD Y <= second_operand
-- 0 1 AND Y <= first_operand and second_operand
-- 1 0 OR Y <= first_operand or second_operand
-- 1 1 XOR Y <= first_operand xor second_operand
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library unisim;
--use unisim.vcomponents.all;
--
entity logical_bus_processing is
Port (first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
clk : in std_logic);
end logical_bus_processing;
--
architecture low_level_definition of logical_bus_processing is
--
-- Internal signals
--
signal combinatorial_logical_processing : std_logic_vector(7 downto 0);
signal sel: std_logic_vector(1 downto 0);
--
begin
sel <= code1 & code0;
bus_width_loop: for i in 0 to 7 generate
--
begin
combinatorial_logical_processing(i) <= (first_operand(i) xor second_operand(i))
when (code1 = '1' and code0 = '1') else
(first_operand(i) or second_operand(i))
when (code1 = '1' and code0 = '0') else
(first_operand(i) and second_operand(i))
when (code1 = '0' and code0 = '1') else
second_operand(i);
pipeline_bit:
process (clk)
begin
if clk'event and clk = '1' then
Y(i) <= combinatorial_logical_processing(i);
end if;
end
process pipeline_bit;
end generate bus_width_loop;
--
end low_level_definition;
--

28
picoblaze.gise

@ -0,0 +1,28 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="picoblaze.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>

684
picoblaze.vhd

@ -0,0 +1,684 @@
-- Constant (K) Coded Programmable State Machine for CoolRunner-II Devices
--
-- Version : 1.00
-- Version Date : 15th August 2002
--
-- Start of design entry : 12th July 2002
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2001. This code may be contain portions patented by other
-- third parites. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- Main Entity for picoblaze
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity picoblaze is
Port ( address : out std_logic_vector(7 downto 0);
instruction : in std_logic_vector(15 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
reset : in std_logic;
clk : in std_logic);
end picoblaze;
architecture Behavioral of picoblaze is
--
-- Size of register bank, stack counter can be changed here
--
constant register_bank_address : natural := 3; -- 8 registers
constant stack_counter_address : natural := 2; -- 4 program stack address
--
-- size of program counter should not be changed
--
constant program_counter_address : natural := 8; -- 256 program word
--
-- Decalare instruction set decoding
--
-- program control group
constant jump_id : std_logic_vector(4 downto 0) := "11010";
constant call_id : std_logic_vector(4 downto 0) := "11011";
constant return_id : std_logic_vector(4 downto 0) := "10010";
--
-- logical group
constant load_k_to_x_id : std_logic_vector(4 downto 0) := "00000";
constant load_y_to_x_id : std_logic_vector(4 downto 0) := "01000";
constant and_k_to_x_id : std_logic_vector(4 downto 0) := "00001";
constant and_y_to_x_id : std_logic_vector(4 downto 0) := "01001";
constant or_k_to_x_id : std_logic_vector(4 downto 0) := "00010";
constant or_y_to_x_id : std_logic_vector(4 downto 0) := "01010";
constant xor_k_to_x_id : std_logic_vector(4 downto 0) := "00011";
constant xor_y_to_x_id : std_logic_vector(4 downto 0) := "01011";
--
-- arithmetic group
constant add_k_to_x_id : std_logic_vector(4 downto 0) := "00100";
constant add_y_to_x_id : std_logic_vector(4 downto 0) := "01100";
constant addcy_k_to_x_id : std_logic_vector(4 downto 0) := "00101";
constant addcy_y_to_x_id : std_logic_vector(4 downto 0) := "01101";
constant sub_k_to_x_id : std_logic_vector(4 downto 0) := "00110";
constant sub_y_to_x_id : std_logic_vector(4 downto 0) := "01110";
constant subcy_k_to_x_id : std_logic_vector(4 downto 0) := "00111";
constant subcy_y_to_x_id : std_logic_vector(4 downto 0) := "01111";
--
-- shift and rotate
constant shift_rotate_id : std_logic_vector(4 downto 0) := "10100";
--
-- added new instruction
-- flip
-- constant flip_id : std_logic_vector(4 downto 0) := "11111";
--
-- input/output group
constant input_p_to_x_id : std_logic_vector(4 downto 0) := "10000";
constant input_y_to_x_id : std_logic_vector(4 downto 0) := "11000";
constant output_p_to_x_id : std_logic_vector(4 downto 0) := "10001";
constant output_y_to_x_id : std_logic_vector(4 downto 0) := "11001";
--
-- interrupt group
--
constant interrupt_id : std_logic_vector(4 downto 0) := "11110";
constant returni_id : std_logic_vector(4 downto 0) := "10110";
--
-- flag
constant zero_id : std_logic_vector(1 downto 0) := "00";
constant not_zero_id : std_logic_vector(1 downto 0) := "01";
constant carry_id : std_logic_vector(1 downto 0) := "10";
constant not_carry_id : std_logic_vector(1 downto 0) := "11";
-- instruction(14) : 0 - constant for 2nd operand, 1 - content of sYY register.
--
------------------------------------------------------------------------------------
--
-- Components used in picoblaze and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- Input and Output Strobes
--
component IO_strobe_logic
Port (i_input : in std_logic;
i_output : in std_logic;
active_interrupt : in std_logic;
T_state : in std_logic;
reset : in std_logic;
write_strobe : out std_logic;
read_strobe : out std_logic;
clk : in std_logic);
end component;
--
-- An 8-bit arithmetic process
--
component arithmetic_process
Port (first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end component;
--
-- Definition of an 8-bit shift/rotate process
--
component shift_rotate
Port (operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
inject_bit : in std_logic;
shift_right : in std_logic;
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end component;
-- added new instruction
--
-- Definition of flip process
--
--component flip
-- Port (operand : in std_logic_vector(7 downto 0);
-- Y : out std_logic_vector(7 downto 0);
-- clk : in std_logic);
-- end component;
--
-- Definition of an 8-bit logical processing unit
--
component logical_bus_processing
Port (first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
clk : in std_logic);
end component;
--
-- Reset conditioning and T-state generation
--
component T_state_and_Reset
Port ( reset_input : in std_logic;
internal_reset : out std_logic;
T_state : out std_logic;
clk : in std_logic);
end component;
--
--
-- Decoding and timing of write enable for register bank and clock enable for flags
--
component register_and_flag_enable
Port (i_logical: in std_logic;
i_arithmetic: in std_logic;
i_shift_rotate: in std_logic;
-- i_flip: in std_logic; -- added new instruction
i_returni: in std_logic;
i_input: in std_logic;
active_interrupt : in std_logic;
T_state : in std_logic;
register_enable : out std_logic;
flag_enable : out std_logic;
clk : in std_logic);
end component;
--
-- Carry Flag logic
--
component carry_flag_logic
Port (add_sub : in std_logic;
shift : in std_logic;
returni : in std_logic;
shift_carry : in std_logic;
add_sub_carry : in std_logic;
shadow_carry : in std_logic;
reset : in std_logic;
flag_enable : in std_logic;
carry_flag : out std_logic;
clk : in std_logic);
end component;
--
-- Zero Flag logic
--
component zero_flag_logic
Port (data : in std_logic_vector(7 downto 0);
returni : in std_logic;
shadow_zero : in std_logic;
reset : in std_logic;
flag_enable : in std_logic;
zero_flag : out std_logic;
clk : in std_logic);
end component;
--
-- Definition of a Program Counter
--
component program_counter
Port (i_jump : in std_logic;
i_call : in std_logic;
i_return : in std_logic;
i_returni : in std_logic;
conditional : in std_logic;
low_instruction : in std_logic_vector(7 downto 0);
stack_value : in std_logic_vector(7 downto 0);
flag_condition_met : in std_logic;
T_state : in std_logic;
reset : in std_logic;
interrupt : in std_logic;
program_count : out std_logic_vector(7 downto 0);
clk : in std_logic);
end component;
--
-- An 8-bit dual port RAM
--
component register_bank
generic(M: natural);
Port ( we : in std_logic;
d_bus : in std_logic_vector(7 downto 0);
wclk : in std_logic;
a : in std_logic_vector(M-1 downto 0);
dpra : in std_logic_vector(M-1 downto 0);
spo_bus : out std_logic_vector(7 downto 0);
dpo_bus : out std_logic_vector(7 downto 0));
end component;
--
-- State_ram
--
component stack_ram
generic(M: natural; N: natural);
Port (Din : in std_logic_vector(N-1 downto 0);
Dout : out std_logic_vector(N-1 downto 0);
addr : in std_logic_vector(M-1 downto 0);
write_bar : in std_logic;
clk : in std_logic);
end component;
--
-- Address pointer for program stack
--
component stack_counter
generic (N: natural);
Port (i_call : in std_logic;
i_return : in std_logic;
i_returni : in std_logic;
conditional : in std_logic;
T_state : in std_logic;
flag_condition_met : in std_logic;
active_interrupt : in std_logic;
reset : in std_logic;
stack_count : out std_logic_vector(N-1 downto 0);
clk : in std_logic);
end component;
--
-- Capture of interrupt signal
--
component interrupt_capture is
Port (interrupt : in std_logic;
T_state : in std_logic;
reset : in std_logic;
interrupt_enable : in std_logic;
active_interrupt : out std_logic;
clk : in std_logic);
end component;
--
-- Interrupt Enable and shaddow flags
--
component interrupt_logic is
Port (i_interrupt : in std_logic;
i_returni : in std_logic;
instruction0 : in std_logic;
active_interrupt : in std_logic;
carry_flag : in std_logic;
zero_flag : in std_logic;
reset : in std_logic;
interrupt_enable : out std_logic;
shaddow_carry : out std_logic;
shaddow_zero : out std_logic;
clk : in std_logic);
end component;
-- internal signals
--
-- instruction decoding signals
--
signal i_jump : std_logic;
signal i_call : std_logic;
signal i_return : std_logic;
signal i_returni : std_logic;
--
signal i_load_k_to_x : std_logic;
signal i_load_y_to_x : std_logic;
signal i_and_k_to_x : std_logic;
signal i_and_y_to_x : std_logic;
signal i_or_k_to_x : std_logic;
signal i_or_y_to_x : std_logic;
signal i_xor_k_to_x : std_logic;
signal i_xor_y_to_x : std_logic;
--
signal i_add_k_to_x : std_logic;
signal i_add_y_to_x : std_logic;
signal i_addcy_k_to_x : std_logic;
signal i_addcy_y_to_x : std_logic;
signal i_sub_k_to_x : std_logic;
signal i_sub_y_to_x : std_logic;
signal i_subcy_k_to_x : std_logic;
signal i_subcy_y_to_x : std_logic;
signal i_add_sub : std_logic;
signal i_carry_nocarry : std_logic;
--
signal i_input_p_to_x : std_logic;
signal i_input_y_to_x : std_logic;
signal i_output_p_to_x : std_logic;
signal i_output_y_to_x : std_logic;
--
signal i_interrupt : std_logic;
--
signal i_arithmetic : std_logic;
signal i_logical : std_logic;
signal i_shift_rotate : std_logic;
signal i_input : std_logic;
signal i_output : std_logic;
-- added new instruction
-- signal i_flip : std_logic;
signal conditional : std_logic;
signal zero : std_logic;
signal not_zero : std_logic;
signal carry : std_logic;
signal not_carry : std_logic;
signal shift_right : std_logic;
signal shift_in_bit : std_logic;
signal shift_code1 : std_logic;
signal shift_code0 : std_logic;
signal logical_code1 : std_logic;
signal logical_code0 : std_logic;
--
-- Fundamental control signals
--
signal internal_reset : std_logic;
signal T_state : std_logic;
--
-- Register bank signals
--
signal sX_register : std_logic_vector(7 downto 0);
signal sY_register : std_logic_vector(7 downto 0);
signal register_write_enable : std_logic;
--
-- ALU signals
--
signal second_operand : std_logic_vector(7 downto 0);
signal logical_result : std_logic_vector(7 downto 0);
signal shift_and_rotate_result : std_logic_vector(7 downto 0);
signal shift_and_rotate_carry : std_logic;
signal arithmetic_result : std_logic_vector(7 downto 0);
signal arithmetic_carry : std_logic;
signal ALU_result : std_logic_vector(7 downto 0);
signal flip_result : std_logic_vector(7 downto 0);
--
-- Flag signals
--
signal carry_flag : std_logic;
signal zero_flag : std_logic;
signal flag_clock_enable : std_logic;
signal flag_condition_met : std_logic;
--
-- Interrupt signals
--
signal shaddow_carry_flag : std_logic;
signal shaddow_zero_flag : std_logic;
signal interrupt_enable : std_logic;
signal active_interrupt : std_logic;
--
-- Program Counter and Stack signals
--
signal program_count : std_logic_vector(7 downto 0);
signal stack_pop_data : std_logic_vector(7 downto 0);
signal stack_pointer : std_logic_vector(stack_counter_address-1 downto 0);
--
------------------------------------------------------------------------------------
--
-- Start of picoblaze circuit description
--
------------------------------------------------------------------------------------
begin
--
-- Connections to output port and port address
--
out_port <= sX_register;
port_id <= second_operand;
--
--
-- Input and Output Strobes
--
IO_strobes: IO_strobe_logic
port map (i_input => i_input,
i_output => i_output,
active_interrupt => active_interrupt,
T_state => T_state,
reset => internal_reset,
write_strobe => write_strobe,
read_strobe => read_strobe,
clk => clk );
--
-- The ALU structure
--
arithmetic_group: arithmetic_process
port map (first_operand => sX_register,
second_operand => second_operand,
carry_in => carry_flag,
code1 => i_add_sub,
code0 => i_carry_nocarry,
Y => arithmetic_result,
carry_out => arithmetic_carry,
clk => clk);
shift_group: shift_rotate
port map (operand => sX_register,
carry_in => carry_flag,
inject_bit => shift_in_bit,
shift_right => shift_right,
code1 => shift_code1,
code0 => shift_code0,
Y => shift_and_rotate_result,
carry_out => shift_and_rotate_carry,
clk => clk);
-- added new instruction
-- flip_group: flip
-- port map (operand => sX_register,
-- Y => flip_result,
-- clk => clk);
logical_group: logical_bus_processing
port map (first_operand => sX_register,
second_operand => second_operand,
code1 => logical_code1,
code0 => logical_code0,
Y => logical_result,
clk => clk);
--
-- Reset conditioning and T-state generation
--
basic_control: T_state_and_Reset
port map (reset_input => reset,
internal_reset => internal_reset,
T_state => T_state,
clk => clk);
--
reg_and_flag_enables: register_and_flag_enable
Port map (i_logical => i_logical,
i_arithmetic => i_arithmetic,
i_shift_rotate => i_shift_rotate,
-- i_flip => i_flip, -- added new instruction
i_returni => i_returni,
i_input => i_input,
active_interrupt => active_interrupt,
T_state => T_state,
register_enable => register_write_enable,
flag_enable => flag_clock_enable,
clk => clk);
carry_logic: carry_flag_logic
Port map (add_sub => i_arithmetic,
shift => i_shift_rotate,
returni => i_returni,
shift_carry => shift_and_rotate_carry,
add_sub_carry => arithmetic_carry,
shadow_carry => shaddow_carry_flag,
reset => internal_reset,
flag_enable => flag_clock_enable,
carry_flag => carry_flag,
clk => clk);
zero_logic: zero_flag_logic
port map (data => ALU_result,
returni => i_returni,
shadow_zero => shaddow_zero_flag,
reset => internal_reset,
flag_enable => flag_clock_enable,
zero_flag => zero_flag,
clk => clk);
--
--
-- Program Counter
--
prog_count: program_counter
port map (i_jump => i_jump,
i_call => i_call,
i_return => i_return,
i_returni => i_returni,
conditional => conditional,
low_instruction => instruction(7 downto 0),
stack_value => stack_pop_data,
flag_condition_met => flag_condition_met,
T_state => T_state,
reset => internal_reset,
interrupt => active_interrupt,
program_count => program_count,
clk => clk );
address <= program_count;
--
-- Register bank
--
data_registers: register_bank
generic map (register_bank_address)
port map (we => register_write_enable,
d_bus => ALU_result,
wclk => clk,
a => instruction(10 downto 8),
dpra => instruction(7 downto 5),
spo_bus => sX_register,
dpo_bus => sY_register );
--
-- Stack RAM
--
stack_memory: stack_ram